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Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Features
- RoHS compliant products.
- JEDEC standard 1.8V ± 0.1V Power supply.
- VDDQ=1.8V ± 0.1V.
- Max clock Freq: 400MHZ; 800Mb/s/Pin.
- Posted CAS.
- Programmable CAS Latency: 3,4,5.
- Programmable Additive Latency :0, 1,2,3 and 4.
- Write Latency (WL) = Read Latency (RL)-1.
- Burst Length: 4,8(Interleave/nibble sequential).
- Programmable sequential / Interleave Burst Mode.
- Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature).
- Off-Chip Driver (OCD) Impedance Adjustment.
- MRS cycle with address key programs.
- On Die Termination.
- Serial presence detect with EEPROM.
Power | |
---|---|
Memory voltage | 1.8 V |
Memory | |
Memory layout (modules x size) | 1 x 1 GB |
Internal memory | 1 GB |
Component for | Laptop |
Memory form factor | 200-pin SO-DIMM |
CAS latency | 5 |
Memory voltage | 1.8 V |
ECC | No |
Memory clock speed | 800 MHz |
Internal memory type | DDR2 |
Features | |
---|---|
Memory layout (modules x size) | 1 x 1 GB |
Internal memory | 1 GB |
Component for | Laptop |
Memory form factor | 200-pin SO-DIMM |
CAS latency | 5 |
Memory voltage | 1.8 V |
ECC | No |
Memory clock speed | 800 MHz |
Internal memory type | DDR2 |
Harmonized System (HS) code | 84733020 |
Logistics data | |
Harmonized System (HS) code | 84733020 |
Other features | |
Harmonized System (HS) code | 84733020 |
SKU | TS128MSQ64V8U | ||||||||||||||||||||||||||||||||||||||||||||||||||||||
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EAN | 7605578112686 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||
Specification |
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Manufacturer | Transcend | ||||||||||||||||||||||||||||||||||||||||||||||||||||||
In Stock | Y |